Contact Info
Email: tejaswinichetty@sistec.ac.in
Ms. Tejaswini Chetty
- Department:
- Designation:
- Qualification:
Prof. Tejaswini Chetty has joined Sagar Group in July 2018. She is M.Tech in Micro-electronics and VLSI design from RGPV Bhopal. She has 7.5 years of academic experience. She has 3 Research Papers to her credit published and presented in various national and international conferences.
Specialization
- Subject: VLSI Design, Electronic Devices and Circuits, Electronic Instrumentation, Signals and Systems, Basic Electronics, Digital Circuits and System etc.
Conference/Workshop Highlights
- International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering”. “Designing of MIPS R2000 Processor on Spartan3E”. in IJAREEIE, Volume 2, Issue 11, November 2013.
- 2nd International Conference on. ‘Soft Computing for Problem Solving’ held during December 28-30, 2012 at JK Lakshmipati University, Jaipur.
- “International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering”. “Designing of Self Immunity Technique for 64 bit Register File against Soft Errors” in IJAREEIE, Volume 2,Issue 4, April 2013.
Career Highlights
- Has 7.5 Years of experience in Academics.
- Guided a number of thesis for M.Tech and B. Tech.
- Participated in various technical seminars and workshops.